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TSMC 65nm Sign-Off

~~SLIDESHOW~~

2009.09.12 TSMC sign-off meeting

TSMC Sign-Off consideration

Timing Closure taking all kinds of effects into account

  • Multi-mode STA → DFT的Corner,Scan mode(shift capture compression)、mbist、bsd and function
  • Multiple device and RC corners →
    • WC WCL1) BC (or LT)
    • CWorst CBest (RCWorst RCBest RCTypical)
    • OCV (hold margin)
    • Crosstalk → PT set si_enable_analysis true
    • CCS models characterized with DFM LPE2)
      • NLDM > 5% error in 65nm and below → error just means pessimistic
    • DFM timing impact - Dummy metals and Redundant VIAs

Corner

  • WC:WCCOM  SS 0.9VDD 125
  • TC:NCCOM  TT 1.0VDD  25
  • BC:BCCOM  FF 1.1VDD  0
  • LT:LTCOM  FF 1.1VDD -40 (用于军事应用,the best)
  • ML: MLCOM  FF 1.1VDD 125(由Isub整体正比于T的平方来看,T越高,leakage power 越大:公式*)
  • TL: TLCOM TT VDD 25
  • WCL:WCCOML SS 0.9VDD -40 (温度反偏效应的影响:低电压时,IDS由VT决定,而VT反比于T,因而当T增大时,VT减小,IDS增加,延时减小,速度更快;高电压时,IDS由u来决定,它反比于T,当T增大时,u减小(因为T增大,晶格振动越大,从而更),IDS减小,延时增大,它取决于工艺节点和阈值电压的大小)

此外如果是Multi Voltage时:

  • Low-v W:WC0D72COM SS 0.72VDD 125
  • Low-v T:TC0D72COM TT 0.8VDD 25
  • Low-V B:BC0D88COM FF 0.88VDD 0

与相应的RC corner相组合:C worst ,C best (RCworst,RCbest RCtypical)

Timing Sign-Off Recommendation

WC+
Cworst
WCL+
Cworst
BC or LT+
Cbest/Cworst
Max TransitionOCVSetup MarginHold Margin
65nmsetup / holdsetup / holdhold0.6ns3)WC: 5%
BC: 10%
Clock jitter50ps

RC Corner Selection

From Resistance Point of view

  • Rmax in Cbest corner is similar to Rmax in RCworst corner
  • Rmin in Cworst corner is similar to Rmin in RCbest corner
  • Choose both Cworst and Cbest as RC corner to cover hold time checks for shorter path
  • As to setup timing check, Recommend to use Cworst only to worst/max delay path (longer paths)
CworstCbestRCworstRCbest
Max R-20.6%20.7%20.7%-20.6%
Min R21%-12.2%-11.8%19.8%
Max C-19%21.3%21.3%-19%
Min C21.2%-13.4%-11.8%19.3%

Ctypical is used as the reference corner of % number

What is OCV

ocv

  • WC: 5%
  • BC: 10%
intra-die device
variation
RC variation 10%
(Cworst - Cbest)
Voltage Variation
(3% VDD+VSS)
Tempture (10C)Total
WC delta %1.40.81.60.44.2
BC delta %3.61.51.61.38.0

Numbers are based on the detailed spice simulation and silicon data of production chips

OCV setting summary

  • only set ocv on clock
    • Not set on data, data path timing is boundary by WC and BC - if set, it would be even worse
  • OCV is process and design dependent
    • Depending on intra-die process and RC variation
    • Depending on clock tree size, routing layers, voltage drop and chip temperture
  • Focus on on-chip clock variation
  • 65nm OCV setting recommendation in PrimeTime
    • WC -5% BC 10%
set_operating_conditions -analysis_type on_chip_variation
set timing_remove_clock_reconvergence_pessimism true
 
#WC corner for setup check
set_timing_derate -early 0.95
set_timing_derate -late 1.0
#BC corner for hold check
set_timing_derate -early 1.0
set_timing_derate -late 1.1

~~DISCUSSION~~

1) WCL:0.9VDD, ss, low tempture
2) layout parameter extraction
3) Max transition applied at WC corner
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